jz4725 design

Carlos Camargo cicamargoba at gmail.com
Sun Aug 23 10:19:49 EDT 2009


On Sun, Aug 23, 2009 at 8:52 AM, W.G. van de Hulst <suyckerbol at gmail.com>wrote:

> 2009/8/22, Carlos Camargo <cicamargoba at gmail.com>:
> > .... We want to make two version of this
> > board one using the same chip on qi_avt2, and another one using the TQFP
> > chip.
> It would be interesting to do a benchmark to see if a jz4725/jz4725b
> has a better SDRAM controller than the much older jz4720 (both running
> at the same speed to be fair).


Yes, we will be make some benchmarks,  when arrived th Nanonote board.


> I think that for many people is easy to build a cheaper and economic
> version
> > with a TQFP chip.
> What to do when you need USB Host (not present on the jz4725, jz4725b
> and jz4755)? Add a separate USB Host or OTG chip?
>

I have a serious problem here, we want to connect an FPGA to the data,
address, ctrl, bus but this chip doesn't have available the RD and WR
signals, there are two signals that maybe we can use BUFD and WE0, WE1

BUFD_: Select CPU to SRAM chip direction in data bi-direction buffer
WE0_: SDR/Static memory byte 0 write enable

But I can't find any timming diagram or waveform for these signals


Carlos


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-- 
Carlos Iván Camargo Bareño
Profesor Asistente
Departamento de Ingeniería Eléctrica y Electrónica
Universidad Nacional de Colombia
cicamargoba at unal.edu.co
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