jz4725 design [FPGA]

Carlos Camargo cicamargoba at gmail.com
Mon Aug 24 08:15:39 EDT 2009


Wolfgang


On Sun, Aug 23, 2009 at 10:32 PM, Wolfgang Spraul
<wolfgang at qi-hardware.com>wrote:

> Carlos,
> did you know that we had a discussion about adding an FPGA to future
> NanoNotes? Deng Ya Nuo in Xi'An proposed it back in
> http://lists.qi-hardware.com/pipermail/developer/2009-July/000072.html
> and it's up on the Ya product page
> http://www.qi-hardware.com/products/ya-nanonote/
>
> Back then Deng suggested to use a Lattice XP2, maybe even the small ones
> XP2-5 or XP2-8 (both available in 8x8mm packaging).
> Which FPGA did you think about?
> Not sure how Deng planned to hook it up into the system.
>

The problem with the jz4725 is that doesn't have the RD & WR signals, but
Sander from ingenic, sent the user manual, this morning so, I think I can
find the information about this connection.

We are using Xilinx FPGA, with xc3sprog, we use processor GPIOs for program
the FPGA.



I do like the idea of adding a small and cheap entry-level FPGA to the
> NanoNotes...


This FPGA will be usefull for FPU or DSP.

Carlos



>
> Wolfgang
>
> On Sun, Aug 23, 2009 at 12:43:05PM -0500, Carlos Camargo wrote:
> > Hi
> >
> >
> > We are thinking connect the FPGA as SDRAM, but is not a natural way,
> maybe
> > is necessary use another chip for that.
> > We also evaluate the conection of our FPGA peripheral as a NAND chip, but
> as
> > i said before we use this board as academic board and we descart this
> > options.
> >
> >
> > Carlos
> >
> >
> >
> > On Sun, Aug 23, 2009 at 11:08 AM, Adam Wang <adam at qi-hardware.com>
> wrote:
> >
> > >  Hi,
> > >
> > >
> > >  > I think that for many people is easy to build a cheaper and economic
> > >> version
> > >> > with a TQFP chip.
> > >>  What to do when you need USB Host (not present on the jz4725, jz4725b
> > >> and jz4755)? Add a separate USB Host or OTG chip?
> > >>
> > >
> > > I have a serious problem here, we want to connect an FPGA to the data,
> > > address, ctrl, bus but this chip doesn't have available the RD and WR
> > > signals, there are two signals that maybe we can use BUFD and WE0, WE1
> > >
> > > BUFD_: Select CPU to SRAM chip direction in data bi-direction buffer
> > > WE0_: SDR/Static memory byte 0 write enable
> > >
> > > But I can't find any timming diagram or waveform for these signals
> > >
> > > Do you want to connect to SDRAM? May reference reversely to waveform of
> > > SDRAM's specifications even it's not a regular rule. :-)
> > > The command interval of read / write is having more details in memory
> spec.
> > > Or is there anyone have known jz47xx experiences of command interval
> here?
> > > Adam
> > >
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> >
> >
> >
> > --
> > Carlos Iván Camargo Bareño
> > Profesor Asistente
> > Departamento de Ingeniería Eléctrica y Electrónica
> > Universidad Nacional de Colombia
> > cicamargoba at unal.edu.co
>
> > _______________________________________________
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-- 
Carlos Iván Camargo Bareño
Profesor Asistente
Departamento de Ingeniería Eléctrica y Electrónica
Universidad Nacional de Colombia
cicamargoba at unal.edu.co
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