Qi avt2 RC3
adam at qi-hardware.com
Wed Dec 2 21:09:21 EST 2009
I didn't see you in the loop last mail, so I pasted Carlos's mail. And added
On Thu, Dec 3, 2009 at 12:14 AM, Carlos Camargo <cicamargoba at gmail.com>wrote:
> Hi Werner
>> It would also be interesting to know what problems you hit in your
>> journey with KiCad and how you solved them. Ah, and are you using
>> fped or did you make the footprints in KiCad (or somewhere else) ?
> The main problem we have was the copper pour areas, Kicad don't use this
> layer for connectivity. We solve this issue wiring the GND and VDD at hand.
> We maka all footprints in kicad, we found fped later :(
> Best Regards
To put this in relation, also the following parameters would be interesting:
- number of layers
- minimum trace width (ah, I see that Adam just answered that :)
- type of vias (micro, through, blind, buried)
- board size
- surface finish (gold, silver, tin, organic, ...)
Much thanks for great suggestions above, since our avt2 is currently 4
layers and some parameters don't necessary in this time; but you are right,
especially the smart phone pcb has almost 8 layers; we had have a doc 
which recorded most of above parameters used to communicate with vendor to
sync both. It's in chinese version, I'll make an english version to the
vendor. The proto type of producing pcb generally has reasonable price.
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