Qi avt2 RC3

Adam Wang adam at qi-hardware.com
Wed Dec 2 23:28:34 EST 2009

Hi Werner,

I extracted some more details from Chinese document for you to our avt2

> To put this in relation, also the following parameters would be
> interesting:
> - number of layers
4 layers

> - minimum trace width (ah, I see that Adam just answered that :)
3.9 mils

> - type of vias (micro, through, blind, buried)
 We have only 4 layers, so we don't have buried and blind vias. Micro vias
is in generally under 5~6 mils, I need check if this new avt2 has. The HDI
pcb maker has micro vias capability normally.

> - board size
 3.724 inches by 3.346 inches

> - surface finish (gold, silver, tin, organic, ...)
> We'll use gold surface electroplate for cob process, so there's no
OSP(Organic Solderability Preservatives) on avt2 board. The gta03 (smart
phone, 8 layers) project before in OM have been used OSP. The tin process
will still have on avt2 board.

Since we are switching to a new vendor now (for the kicad files), the good
news is that the new vendor will have all communication in English, I'll
make an English version check list for the new vendor and of course we will
publish all files.
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