Add VOIP application to Qi series..

W.G. van de Hulst suyckerbol at gmail.com
Sun Jul 26 04:57:43 EDT 2009


OK, a little bit about Moore:  his new company (GreenArrays) is
designing chips with 4, 32 and 40 very simple cores, for instance the
first one will be the GA32:

http://www.colorforth.com/GA32.htm

1.8V Vdd +- 10%
3 mA per node that's running; 100 nA if sleeping (leakage)

His previous company produced the S40 (40 cores), but there are patent
wars going on between them and (according to him) the status and
future of S40 chips is unclear:

http://www.colorforth.com/S40.htm

I have trouble mapping encryption, inherently sequential, to a
rectangle of these cores, but I think you can at least use pipelining
to get a speedup. This is like laying out a floor plan by assigning
stages to cores and connecting them. The following article has some
background and an example:

http://www.ddj.com/hpc-high-performance-computing/210603608

Because each core can run at up to 600 (700?) MHz and the next core or
stage doesn't use much power while waiting, this might work (perhaps
even brilliantly so). But OTOH maybe the constraints of the c18 core,
including its 18-bit integer arithmetic, are too severe.




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