adam at qi-hardware.com
Thu Jul 30 23:04:37 EDT 2009
> So I naturally wonder if the R/W signal for the LCD on the SoC is
> connected to the LCD for syncing, and if not, if that can still be
> fixed at this late stage.
There's a book called "Video Demystified A handbook for digital engineer
by Keith Jack" which modernly described about all
video signals formats, you can easily google it for full pdf file or buy it.
Video applications somehow if follow reference design supposed that
should get normally display ignoring video signals layout firstly.
Mostly need to probably know is the analog video rather than digital
video format. e.x. blanking(H/V synchronization) and active line(visible
There're several registers settings based on those theories. For NTSC
system, some h/w designs followed variably on 8-wires digital signals, 2
and 1 pclk (for example 27MHz)...then another h/w designs use 16-wires,
4 syncs(H sync / V sync / Frame / half of V) and 1 pclk( now down to
Those are based on the video formats.
so maybe take a quick look on:
1, what kind of h/w structures related to video format it used (ITU-R
BT601 or 656 or others)
2, reference to the digital parameters table for LCD's resolution like
also (16:9 / 4:3 aspect ratio, active horizontal samples, frame rate,
1*Y sample rate, total horizontal samples, horizontal blanking samples),
those may be are hard to understand but codes base should be normally
well-defined already to relevant resolution, most time you need to FINE
tune EAV and SAV registers, rising edge or falling edge setting and a
few of others.
3, if those above are confirmed then start to check h/w layout...but
somehow it's hard to developers...because of some "tearing" or "not
sync" unexpectedly came from wrong layout arrangement of cross btw high
and low digital signals. It's hard to try to investigate from schematic.
of course an good stack on s/w three buffers are also the keys for
debug...but probably check the founded first.
Hope this can help you.
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