Lattice or Xilinx
cicamargoba at gmail.com
Thu Sep 10 08:14:41 EDT 2009
> The lowest power I know are actualy CPLDs (coolrunner by Xilinx). That
> means they have non-volatile configuration and have less logic resources as
> compared to FPGAs.
But, the logic capacity is very low, but may be enough for some
> 1- Connector (huge if you want to make all those I/O pins useful).
> 2- A CPLD to connect the FPGA programming interface to the SoC.
> 3- Power regulators (for example, Spartan 6 use 1.2V core voltage), and
> possibly power management circuitry too to save power when no in use.
> The CPLD is not necessary, as I said before you can use some processor GPIO
pins for JTAG programming.
And no matter what FPGA/connector you choose you won't fullfill the needs of
> all the potential users, which I believe will be anyway a minority in the
> whole user base.
I agree, I think that if place an internal connector with D0-D15, A0-A14,
RD, WR, CSX, and some GPIOs many people (like me ) can build his own boards
with any CPLD.
The USB port idea is very good, we can design some reference boards, for use
Carlos Iván Camargo Bareño
Departamento de Ingeniería Eléctrica y Electrónica
Universidad Nacional de Colombia
cicamargoba at unal.edu.co
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