Lattice or Xilinx
wolfgang at qi-hardware.com
Thu Sep 10 10:21:58 EDT 2009
Ignacio and Carlos,
the FPGA discussion is actually a good way to better explain some of our
plans at Qi Hardware.
We believe in open innovation, and we believe in delivering real value
to real people asap. These two are always a bit at odds with each
other, maintaining the balance will be a big challenge for the Qi
With 'open innovation', we mean to take the best that the open community
has developed, package it, and have it solve real problems of non-technical
people today. While at the same time not cutting off the cycle of further
_open_ innovation. Does that make sense?
So we would not want to add a closed GUI on top of our open kernel.
Or closed hardware underneath our open kernel.
But while we strive for 100% openess (and copyleft to get some power behind
it), we also have a razor-sharp focus on solving real problems in real life.
Qi Hardware is not a supplier of geek toys.
The list of ideas at the Ya NanoNote page is becoming impressive:
But these are not all the things we will add, which would turn the NanoNote
into the ultimate jack-of-all-trades, and guaranteed failure.
These are all the things we want to keep the device open for! Maybe these
are all the things we will not do, and someone else can take and produce
a derivative device.
Will we add a power-hungry, space-consuming and expensive FPGA to all Ya
NanoNotes, even though it may only serve a real purpose for 1% of our
NanoNote buyers? Of course not!
But at the same time we believe in open innovation, and the innovation
needs to come from somewhere. So one idea could be to only make a few
small, ideally zero-cost improvements from the Ben to the Ya NanoNote.
Routing a few more pins to test points, adding USB host (which is only
another connector since it's already in the SoC), increasing SDRAM
to 64 MB. But that would be it.
And then we make a small-volume 2nd variant of the PCB. A 'hacker PCB'
that would fit into the case, but you would have to cut a hole into
the case on one side, and the hacker PCB would stick out by a few
Then that 'excess' PCB space could be filled with connectors, FPGA,
etc. It would be ugly, but not uglier than an open Arduino board for
example. We could make 500 of these hacker PCBs, or 1000, however
large we are able to grow our developer community.
But the main mass-market Ya NanoNote would not be affected.
That one would still be a cheap, polished, low-cost computing device,
delivering to the world the very best the free software and free culture
scene have developed.
Powered by a Linux kernel, offering Wikipedia, Wiktionary, OpenStreetMaps,
MPlayer and other useful free software apps. As much as we can package and
deliver in good quality.
Does all of this make sense? Do we even all agree? Qi Hardware is young,
so some of these thoughts are not battle tested yet, but I believe it's
more or less the direction we are heading to.
I hope it explains why we happily discuss FPGA chips, but at the same
time are focused on making cheap mass-market devices.
Feedback very welcome,
On Thu, Sep 10, 2009 at 01:53:18PM +0200, Ignacio García Pérez wrote:
> 2009/9/10 Wolfgang Spraul <wolfgang at qi-hardware.com>
> > Ignacio,
> > > I would say that for a portable device the MOST important feature, by
> > far,
> > > is the power consumption, and even the latest low power devices have
> > > comparatively (to ASICs) high power requirements.
> > What are the lowest power consumption FPGAs you know about? How much power
> > do they consume?
> The lowest power I know are actualy CPLDs (coolrunner by Xilinx). That means
> they have non-volatile configuration and have less logic resources as
> compared to FPGAs.
> > I think one idea was to just leave an unpopulated place for an FPGA on the
> > board, so we could still sell the device to regular users, but it would
> > have an easily accessible FPGA option for hacking projects.
> Do you really have so much spare real state on the PCB ?.
> Note also that you need room not only for the FPGA itself but also for:
> 1- Connector (huge if you want to make all those I/O pins useful).
> 2- A CPLD to connect the FPGA programming interface to the SoC.
> 3- Power regulators (for example, Spartan 6 use 1.2V core voltage), and
> possibly power management circuitry too to save power when no in use.
> And no matter what FPGA/connector you choose you won't fullfill the needs of
> all the potential users, which I believe will be anyway a minority in the
> whole user base.
> > Or we offer two versions, one with and one without FPGA?
> In order to make that practical you'd need to share same form factors,
> enclosure, etc, and thus you'd be making the device possible larger than
> Seriously, I don't think the potential user base for tinkering justifies the
> inclusion of an FPGA in the design. If you want to provide extensive I/O
> capability, just add a host USB port. Supply of external power IS A MUST,
> but 100mA would be more than enough (and should be switchable from the SoC).
> And it must be a separate USB port, different from the device port used to
> connect to the PC. I you want to go a bit more far, add an special connector
> with I2C, SPI and power.
> That is more than enough for the average hacker. If your project is so
> complex or needs so much bandwidth that hostUSB+I2C+SPI is not enough,
> neither the FPGA would have been (assuming and low-end, cheap and
> non-power-hungry FPGA).
> P.S: got the Ingenic docs. Just haven't had time to properly review them.
> Qi Developer Mailing List
> Mail to list (members only): developer at lists.qi-hardware.com
> Subscribe or Unsubscribe: http://lists.qi-hardware.com/cgi-bin/mailman/listinfo/developer
More information about the discussion