64MB RAM chip for Ya NanoNote

Carlos Camargo cicamargoba at gmail.com
Tue Sep 15 08:08:20 EDT 2009


Hi

>From SDRAM's Data-sheet [1] pag 8:
Address: A0 - A12, BA0, BA1   13 lines for Columns, 10 for Rows.

pag 16:

DQML, DQMH:
Input/output mask: DQM is an input mask signal for write accesses and an
output
enable signal for read accesses. Input data is masked when DQM is sampled
HIGH
during a WRITE cycle. The output buffers are placed in a High-Z state
(two-clock
latency) when DQM is sampled HIGH during a READ cycle. On the x4 and x8,
DQML
(Pin 15) is a NC and DQMH is DQM. On the x16, DQML corresponds to DQ0–DQ7,
and DQMH corresponds to DQ8–DQ15. DQML and DQMH are considered same
state when referenced as DQM.



>From JZ4740 DataSheet:

Byte enable 0
                WE0# / For non-byte-control static memory , D7-0 write
enable signal,
                BE0# / For byte-control static memory , D7-0 selection
signal
                DQM0 / For SDRAM, D7–D0 selection signal
Byte enable 1
               WE1# / For non-byte-control static memory , D15-8 write
enable signal
                BE1# / For byte-control static memory , D15-8 selection
signal
                DQM1/  For SDRAM, D15–D8 selection signal


So, this memory use the same number of rows, and one more column bit that
32MB memory, If you change to:

ROWADDR = 13    #Row address width in bits (11-13)
COLADDR = 10     #Column address width in bits (8-12)

In usbboot config file you can use 64MD SDRAM


Best Regards


[1] http://download.micron.com/pdf/datasheets/dram/sdram/512MbSDRAM.pdf


On Tue, Sep 15, 2009 at 3:17 AM, Adam Wang <adam at qi-hardware.com> wrote:

> Hi,
>
> Wolfgang Spraul wrote:
>
>> Adam,
>> (Carlos already went to sleep in Colombia, so I am posting his suggestion
>> from jabber here...)
>>
>> Carlos said it might be relatively easy to upgrade the SDRAM chip on our
>> board to this one to get 64 MB memory:
>> http://www.micron.com/products/partdetail?part=MT48LC32M16A2P-75
>>
>>
>>
> this micron's part is 8 Meg * 16 * 4 banks = 512Mbit, should use 15 wiring
> addressing (A0~A12, A13/A14) to manage 4 banks, so this is 32M for 16 bits
> data line.
> of course it can be configured 64M but for 8 bits length = 16 Meg * 8 * 4
> banks,
>
>> Do you think it will work?
>> Can we use it as a drop-in replacement on AVT2, or do you have to make
>> changes?
>>
>>
> From the jz4720 datasheet, it shpws A0~A14 can be used as for SDRAM, so
> MT48LC32M16A2P should be drop-in for 32M for 16 bits data line.
> But A15 pin(PB15) will be as for NAND flash command latch if using nand, so
> this is the jz4720's limitation on pin allocation.
>
> if find a 64M for 16 bits data line, it can not replace directly on avt2's
> design, have to make change; like Ingenic's reference design to use dual 32M
> SDRAM with
> extra two GPIOs to allocate and assign the UDQM/LDQM pins of SDRAM, and
> then can reach 64M capacity.
> Adam
>
>  Wolfgang
>>
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-- 
Carlos Iván Camargo Bareño
Profesor Asistente
Departamento de Ingeniería Eléctrica y Electrónica
Universidad Nacional de Colombia
cicamargoba at unal.edu.co
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