64MB RAM chip for Ya NanoNote

Andrés Calderón andres.calderon at emqbit.com
Tue Sep 15 08:24:50 EDT 2009


On Tue, Sep 15, 2009 at 3:17 AM, Adam Wang <adam at qi-hardware.com> wrote:
> Hi,
>
> Wolfgang Spraul wrote:
>>
>> Adam,
>> (Carlos already went to sleep in Colombia, so I am posting his suggestion
>> from jabber here...)
>>
>> Carlos said it might be relatively easy to upgrade the SDRAM chip on our
>> board to this one to get 64 MB memory:
>> http://www.micron.com/products/partdetail?part=MT48LC32M16A2P-75
>>
>>
>
> this micron's part is 8 Meg * 16 * 4 banks = 512Mbit, should use 15 wiring
> addressing (A0~A12, A13/A14) to manage 4 banks, so this is 32M for 16 bits
> data line.
> of course it can be configured 64M but for 8 bits length = 16 Meg * 8 * 4
> banks,
>>
>> Do you think it will work?
>> Can we use it as a drop-in replacement on AVT2, or do you have to make
>> changes?
>>
>

> From the jz4720 datasheet, it shpws A0~A14 can be used as for SDRAM, so
> MT48LC32M16A2P should be drop-in for 32M for 16 bits data line.
> But A15 pin(PB15) will be as for NAND flash command latch if using nand, so
> this is the jz4720's limitation on pin allocation.
>
> if find a 64M for 16 bits data line, it can not replace directly on avt2's
> design, have to make change; like Ingenic's reference design to use dual 32M
> SDRAM with
> extra two GPIOs to allocate and assign the UDQM/LDQM pins of SDRAM, and then
> can reach 64M capacity.
> Adam
>>

Hi,

In the AVT2 are connected 13 address lines between de JZ4720 and the
SDRAM, enough for the row addressing of 64MBytes (16 bits) SDRAM.

Number of addressing lines of de 512Mb SDRAM (32Mwords x 16 bits):
  Row addressing A0-A12 (AVT2 compliant)
  Columns  addressing A0-A9  (AVT2 compliant)
  Bank  addressing BA0-BA1   (AVT2 compliant)

    Andrés Calderón
    Cel:     +57 (300) 275 3666
    Email: andres.calderon at emqbit.com
    Web:    www.emqbit.com


>> Wolfgang
>>
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>
>
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