Xué progress report

Kristoffer Ericson kristoffer.ericson at gmail.com
Fri Aug 20 04:07:50 EDT 2010


On Thu, Aug 19, 2010 at 09:10:59AM -0500, Andrés Calderón wrote:
> On Thu, Aug 19, 2010 at 9:07 AM, Andrés Calderón <andres.calderon at emqbit.com
> > wrote:
> 
> > Hi,
> >
> > A little progress since the last time.
> >
> > 1. DDR series terminators added.
> >
> > 2. Power supply  ICs has been selected:
> >
> >    AIT A7108  for 1.2V, 3.3V and CIS Voltage (800mA):
> >    http://www.ait-ic.com/uploads//2010-03/17/_1268812841_xznfcv.pdf
> >
> >    AIT A7130 (or A7131 )  for 2.5V (3A)
> >    http://www.ait-ic.com/uploads//2010-07/09/_1278642893_dkkew3.pdf
> >
> >    For power management and external watchdog an AVR  ATTINY24 has been
> > selected.
> >
> >
> Just another image:
> http://en.qi-hardware.com/wiki/Xue/layout
> 

Sweet :)


>     Andrés Calderón
> 
> 
> 
> > 3. An finally, the routing process just begin.
> >
> >
> > Regards,
> >
> >     Andrés Calderón
> >     Cel:     +57 (300) 275 3666
> >     Email: andres.calderon at emqbit.com
> >     Gtalk:  andresfcalderon at gmail.com
> >     Web:    www.emqbit.com
> >
> >
> >
> >
> >
> >
> > On Sun, Aug 15, 2010 at 2:00 AM, Andrés Calderón <
> > andres.calderon at emqbit.com> wrote:
> >
> >> On Sat, Aug 14, 2010 at 10:19 AM, Sébastien Bourdeauducq <
> >> sebastien.bourdeauducq at lekernel.net> wrote:
> >>
> >>> On Saturday 14 August 2010 16:57:58 Andrés Calderón wrote:
> >>> > Just the initial placement:
> >>> > http://en.qi-hardware.com/wiki/Xue/layout
> >>>
> >>> Where are you planning to put the series termination resistors for DDR?
> >>> If you are concerned about space, you may want to use resistor packs
> >>> instead
> >>> of discrete 0402 resistors. They also have the added benefit of making
> >>> track
> >>> lengths potentially smaller. I did not use them on Milkymist One because
> >>> they
> >>> make hand rework of the board more difficult, and would not bring a
> >>> significant space improvement (what use the most space is the I/O
> >>> connectors).
> >>>
> >>
> >> I still do not know what DDR terminators are going to use ... probably
> >> array resistors at bottom PCB side.
> >>
> >>
> >>
> >>>
> >>> Still, I would put the DDR chips further apart from the FPGA in order to
> >>> be
> >>> able to place those resistors, and on the same side of it since the
> >>> address
> >>> and control pins need to be shared on both chips - and running those
> >>> traces
> >>> under the BGA isn't the best thing to do because this area is typically
> >>> very
> >>> dense already.
> >>>
> >>> If you have I/O pins to spare and feel like experimenting stuff, you can
> >>> also
> >>> not share those pins and connect them to different FPGA pins. This leaves
> >>> open
> >>> the option of using two independent DRAM channels, which, depending on
> >>> your
> >>>
> >>
> >> We already have independent channels.  The DDR0 has been attached to the
> >> S6 bank3 and the DDR1 to the bank0.
> >>
> >> memory access pattern and DRAM control algorithm, may improve the maximum
> >>> bandwidth you can squeeze out of the memory chips. At least recent NVIDIA
> >>> GPUs
> >>> use this technique, and connect their processor array to a series of
> >>> fully
> >>> independent DRAM controllers through a crossbar switch (pretty hardware
> >>> resource intensive).
> >>>
> >>
> >> Very nice. The dual channel will allow us to make an interesting
> >> exploration of architectures.
> >>
> >>
> >>
> >>>
> >>> S.
> >>>
> >>
> >> Thanks Sébastien, your comments are very valuable.
> >>
> >>
> >> Regards,
> >>
> >>     Andrés Calderón
> >>     Cel:     +57 (300) 275 3666
> >>     Email: andres.calderon at emqbit.com
> >>     Gtalk:  andresfcalderon at gmail.com
> >>     Web:    www.emqbit.com
> >>
> >>>
> >>> _______________________________________________
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> >>>
> >>
> >>
> >

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