memory bandwidth (was Re: JZ4750 driving large displays?)

Werner Almesberger werner at openmoko.org
Fri Aug 20 08:18:17 EDT 2010


S?bastien Bourdeauducq wrote:
> If the Xburst is a standard (no special memory copy/set instructions, no
> write 
> buffer, etc.) in-order pipelined processor, memory latencies can drastically 
> limit the maximum bandwidth it can use.

This memset benchmark should be quite friendly when it comes to not
needing much sophistication in the memory/cache subsystems.

> How did you compute that estimate?

First I looked up the CPU clock. Ingenic's data sheet says 240 MHz,
Sharism's marketing information says 336 MHz. I chose to believe
the latter, which also coincides with the BogoMIPS reported in
/proc/cpuinfo.

(I actually misread CCLK to be 366 MHz, hence the overly small
allowance for overhead, below.)

Then I dumped CPCCR and looked up the MCLK divider. Its value is 2,
meaning a division by 3. I chose to ignore the confused textual
description of what the clocks are derived from in section 5.2.3 of
Jz4740_pm and trusted figure 5-1 instead, obtaining 112 MHz.

I rounded this down to 100 MHz, to allow for a bit of overhead.
(Address setup and such. This should be larger, maybe 30-40%.)

Then I looked up the bus width in the schematics and found it to be
16 bits. Confirmed by Jz4720_ds and the SDRAM data sheet. All
sources agree on the memory being SDR, too.

I didn't check the burst settings.

Revised estimate: 88-145 MB/s for large write bursts, probably
about 130 MB/s.

- Werner




More information about the discussion mailing list


interactive