memory bandwidth (was Re: JZ4750 driving large displays?)

Werner Almesberger werner at openmoko.org
Fri Aug 20 21:21:18 EDT 2010


S?bastien Bourdeauducq wrote:
> You can't really make such an estimate without knowing more about the memory 
> system architecture. Here are two extreme cases.

Hmm, do you have the manuals for the Ingenic CPUs ? If not, Wolfgang
could send them to you. They're kinda semi-non-public :-(

According to table 2-1 of Jz4740_pm. The D-cache (only one, it seems),
is write-back, 16 words write buffer. Given the short treatment it
receives in the manual, it's probably a "standard" MIPS core design.

> Both scenarios are possible with the little information available about the 
> Xburst memory architecture, and their outcome differ greatly. The real case 
> seems to be between the two...

So my estimates are indeed in the "sane" range. Thanks !

Also the change I've observed after disabling the display clock
suggests that the memory system, at least between internal bus and
the SDRAM, is capable of achieving throughputs above 100 MB/s.
(Otherwise, the difference caused by the change would have had to
be larger.)

Meanwhile, I learned something interesting, namely that the old
gmenu2x used to play with the clocks. After disabling gmenu2x on my
Ben, I now get about 60 MB/s with display refresh active, which is
close enough to the speeds others have reported (Rafa with jlime:
65 MB/s, "viric" with nixpkgs: 64 MB/s).

Interestingly, when I compile the benchmark with -march=mips32r2,
it gets faster by about 2 MB/s.

- Werner




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