KiCad - what to commit to revision control, and what not to commit
Werner Almesberger
werner at openmoko.org
Sun Aug 22 13:31:37 EDT 2010
Yanjun Luo wrote:
> 1. How to verify the design? Does the PCB same as the net list?
Do you mean the design rules check (DRC) ? It's the circle with a
checkmark icon in the top icon bar of pcbnew.
eeschema has a similar test, the ERC (Electric Rules Check), with
the same icon.
> 2. How to generate the right gerber files.
To generate Gerber files, open the plot dialog, File > Plot or by
clicking on the plotter icon, also in the top icon bar. There, you
can select among a lot of options, including the plot format. A
useful option is "Exclude pcb edge layer", which prevents the
board outline from being propagated to the copper layers.
- Werner
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