J1 -- very small & simple CPU for an FPGA

David Kuehling dvdkhlng at gmx.de
Fri Dec 3 08:07:41 EST 2010


>>>>> "Sébastien" == Sébastien Bourdeauducq <sebastien.bourdeauducq at lekernel.net> writes:

> On Thursday 02 December 2010 12:51:16 David Kuehling wrote:
>> if you are interested in this kind of extremely compact FPGA CPUs,
>> you might like this one, too:
>> 
>> http://opensource.zylin.com/zpu.htm
>> 
>> Pretty professional, even a GCC toolchain is available, and
>> BSD-licensed.  This also uses a zero-operand architecture
>> (i.e. operands on hardware-stack), so one might call it a "forth"
>> cpu.

> Tried it for the Milkymist USB controller and quickly dropped it
> (designing using my own AVR clone to replace it). It basically looks
> like a contest winner for the slowest and most inefficient CPU you can
> promote with a straight face.

It's not like the developers are praising their CPU to be a performance
competitor for a pipelined risc architecture [1]

  "zpu_core_small.vhd should be ca. 1 DMIPS and zpu_core.vhd should
  yield about 5-10 DMIPS before adding instructions runs out of steam."

  "Achieving above 50-100 DMIPS with the current ZPU architecture is
  probably a non-starter and a more conventional RISC design makes more
  sense here.

  The unique advantages of the ZPU is size in terms of HDL & code
  size. "

Could you at least state which version and configuration of the many many
possible ZPUs you ran (zpu4 small vs. medium, values for generics like
FAST_FETCH, ENA_LEVEL0 thru 2)?  

> As it turned out, that piece of crap takes more than 256 clock cycles
> per byte for a rather simple buffer copy code... It failed to feed the
> data to my USB UART operating at 1.5Mbps while the CPU itself was
> running at 48MHz. That's ludicrous.

Given how the ZPU is designed to "emulate" optional instructions in case
they're stripped from the design to save logic blocks, I dont't doubt
that it is possible to make it that slow.  For me the question is still,
whether it /has/ to be that slow.

> By the way, why is it always poor or stupid designs that make hackaday
> and all the buzz? I've read countless times about this J1, Plasma,
> another crappy AVR clone and ZPU.

Why is it that pople keep ranting about open source designs that nobody
forced them to download or use?  It's not like you paid for it so why
the disappointment?  You could at least supply people with a
reproducable test case that proves the performance problem and makes it
possible to track down, maybe solve the issue.

cheers,

David

[1] http://repo.or.cz/w/zpu.git?a=blob_plain;f=zpu/docs/zpu_arch.html;hb=HEAD#architecture
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