J1 -- very small & simple CPU for an FPGA
sebastien.bourdeauducq at lekernel.net
Fri Dec 3 08:55:00 EST 2010
On Friday 03 December 2010 14:07:41 David Kuehling wrote:
> Could you at least state which version and configuration of the many many
> possible ZPUs you ran (zpu4 small vs. medium, values for generics like
> FAST_FETCH, ENA_LEVEL0 thru 2)?
It was the Verilog version, which does not have those parameters.
> > As it turned out, that piece of crap takes more than 256 clock cycles
> > per byte for a rather simple buffer copy code... It failed to feed the
> > data to my USB UART operating at 1.5Mbps while the CPU itself was
> > running at 48MHz. That's ludicrous.
> Given how the ZPU is designed to "emulate" optional instructions in case
> they're stripped from the design to save logic blocks,
That emulation (and the general ZPU design) uses SRAM blocks for the
microcode, which isn't a free resource either. The logic block utilization
alone does not account for the true cost of the design.
> > By the way, why is it always poor or stupid designs that make hackaday
> > and all the buzz? I've read countless times about this J1, Plasma,
> > another crappy AVR clone and ZPU.
> Why is it that pople keep ranting about open source designs that nobody
> forced them to download or use?
1. I've wasted my time trying ZPU.
2. I do not want other people to do the same, so now they can find that e-mail
and know what to expect. I knew ZPU wasn't going to be fast, but I didn't
think it would be so slow either.
> You could at least supply people with a reproducable test case that proves
> the performance problem and makes it possible to track down, maybe solve the
That was C code with something like:
*uart_tx = buffer[i];
I'll let you figure out the details. I have no more time to spend on processors
that fail to meet my (reasonable) performance goals by one order of magnitude
(I'll want 12Mbps full-speed USB later), and more than enough work dealing
with my own designs.
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