J1 -- very small & simple CPU for an FPGA

David Kuehling dvdkhlng at gmx.de
Sun Dec 5 09:03:49 EST 2010


>>>>> "Sébastien" == Sébastien Bourdeauducq <sebastien.bourdeauducq at lekernel.net> writes:

> On Friday 03 December 2010 14:07:41 David Kuehling wrote:
>> Could you at least state which version and configuration of the many
>> many possible ZPUs you ran (zpu4 small vs. medium, values for
>> generics like FAST_FETCH, ENA_LEVEL0 thru 2)?

> It was the Verilog version, which does not have those parameters.

Maybe that's the problem.  That version does not have much in common
with the vanilla VHDL ZPU implementation (other than the instruction
set).

http://repo.or.cz/w/zpu.git/blob/HEAD:/zpu/hdl/avalanche/readme.txt

so maybe there's a chance that the ZPU is not generally "stupid" or
"crap" after all?

cheers,

David
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