Some Questions on the SIE Xburst-FPGA Interface
Andres Mauricio Asprilla Valdes
amasprillav at unal.edu.co
Mon Dec 27 15:46:01 EST 2010
Hi Cristian. I think this can help you. I implemented an UART interface in the SIE FPGA and I did the linux driver to read and write data to a chip that managed a capacitive keyboard See http://en.qi-hardware.com/wiki/Teclado_Capacitivo for reference. The data is send at 9600 baud with 8 data bits and 1 stop bit. You can see how I read the data and send it to the kernel space that recognised that UART as /dev/ttyFPGA.
The files are located in http://projects.qi-hardware.com/index.php/p/nn-usb-fpga/source/tree/master/UART. I used it when I was in the embedded system course. And it uses the IRQ_F pin to attend the interruption request when the UART module in the FPGA receives a data from RxD pin. Here in the logic folder you can see the HW implementation and in the src folder you can see the Linux driver.
I hope that it helps a lot for your project!
Date: Mon, 27 Dec 2010 10:32:33 -0500
From: Cristian Paul Pe?aranda Rojas <paul at kristianpaul.org>
Subject: Some Questions on the SIE Xburst-FPGA Interface
To: discussion at lists.en.qi-hardware.com
Cc: cicamargoba at gmail.com
Message-ID: <20101227153233.GD2407 at micro.kristianpaul.local>
Content-Type: text/plain; charset="us-ascii"
I got a SIE some moths ago, with the idea of work around a data
aquisition module for a sofware stack implementation for a GPS IF Chip.
I sucefully implemented the serial to parallel module, in order have
data represented as 8 or even 16 bits, and now i want transfer it to
the Xbusrt CPU in SIE, in order to get a raw data and process it latelly.
I was reading the SIE FPGA Xburst docs at QI wiki, but i have some questions
for my particular needs:
1) Send data in just only one way, i mean the Xburst CPU wil read data
from FPGA (mapped as rom-like device)
2). The data i'm sending is arranged in 8bits (it could be increased but
i wanted to stick on the current data-bus width avaliable in SIE Bus)
3). Data will be transfer at around 1MSPS wich is equivalent to 1MB/s
with no interrupt
4). To be sure data is transfered correctly i alredy have a second
register wich turn to HIGH when data is redy to be read/send.
1) SIE Xbusrt FPGA interface uses a CS and RDWR signal in order to write
and read, data, write seems not so much deal considering the
implementation of pulse generator in FPGA. But when talking about
reading data i may not be fully undertood the process but i have the
- Data is read as it is but more than once times (from 7 to
even 100 !!), i already
read parts on ingenic manuals wich refers to SMCR2 register,
is still trying with different TAW and TAS bits but still
dint get in to it, (any advise about syncking data from
timing is wellcome :-))
I also founded a IRQ_F signal wich is wired from FPGA to LCD_15 (Shared
signal ??) pin in the Xbusrt CHIP, i guess this signal can be used for SYNCING data
to be read from the Xbusrt chip, but even if i get the way to use it
wichout affect LCM, i'm not sure if IRQ at the data transfer i need is
the best way or was this signal intented for a soft-irq implementation?
so far i just saw in the Examples the signal is defined but never used.
Why so much trouble if i can implement a buffer? :-).
Well, i could do that as well and will eliminate my part of my problems,
but i just wanted to keep a bit simpler my setup, seems not posible at
Estudiante de Ingeniería Electrónica
Universidad Nacional de Colombia - Sede Bogotá
email: mauricioasprilla1 at gmail.com, amasprillav at unal.edu.co
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