Some Questions on the SIE Xburst-FPGA Interface

Cristian Paul Peñaranda Rojas paul at kristianpaul.org
Mon Dec 27 18:12:59 EST 2010


On Mon, Dec 27, 2010 at 01:19:37PM -0500, Erwin José Lopez Pulgarin wrote:
> Yes, its an IRQ signal you can implement, maybe with your register going
> HIGH you mentioned before or something else. An implementation example is
> available here for the FPGA [2].

If theorically if implement this softIRQ signal, that will be like a read
request from the slave fpga, i probably just resolve on part of the
situation, because:

   I still need to implement a N bytes buffer

   or

   Modify my verilog core to fit the avaliable timings configurations
   in order to fit the TAW (Acess Wait Time Value).

Why i keep rouding about the same, well i just wanted to reduce latency
for the sample as much as i can, BUT i MUST realize the FPGA is in share
bus so either way there must be a latency while reading, 

So a combination of softirq plus a 2028bytes buffer seems the best deal
i can find so far :-)


> Depends on the eye viewing you design, for me it is a little more complex,
> but after using it soo much, I now think its great to use (the primitives of
> FPGA are very useful to implement this buffers).

I jump to this way of doing first to avoid use fpga-specific stuff
like the RAM16 bit definition in former SIE code examples,
So i otught why not just a couple of registers, well you comments and
the reading i did to the "Static Memory Interface" for Xbusrt JZ4525
chip, show thats is more eficient and faster do a reading of a Buffer by
adressing than waiting data byte per byte (my initial tought), and is
eveb more recommended in my setup wich want to avoid less latency
between transmited data.


> 
> Finally, if you are brave enough, you could see a beta implementation of the
> project I am working of robotics (beta is too much to say, it works, but
> because for Christmas gift my development system and all my data were
> deleted :--(  I couldn't publish the last versions), it expands and use the
> control scheme that prof camargo suggested, is a little messy for now (I
> didn't delete the build files, rooky git mistake XD ), but it will get
> better.[3]

Sure why not, can you introduce me a bit more for porpuse of it?
> 
> I hope my humble advices and experience could serve you of some good.

 Sure, big help from your side !
Thanks for your support

Saludos

Cristian Paul

BTW: Will be nice have people involved with SIE and
Electronics/Mechanical stuff more often around at qi-hardware irc
channel, (just saying)

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