[layoutnote]avt2_RC2_20100126

Adam Wang adam at sharism.cc
Mon Feb 1 23:10:39 EST 2010


Hi Carlos,

Now I know what you fixed on .brd file, but they are not I pointed.
Sorry that we misunderstood each other. I am not describing the
errType 19 or 23. Actually I was trying to say the "single" copper
layer. There's short condition together on KEYIN7 and GND. Maybe my
descriptions were not very well. But please see in detail. Especially
in the one "copper" and "drill" layer only. Need to "plot" them to
see.

http://en.qi-hardware.com/wiki/Layout_notes_avt2_RC2_20100202

It's nice you tried to use very small "circle" to build bigger space
to avoid errType 19 and 23.

btw; after I plot gerbers, in the SilKs_Cop layer now is messy. I did
not commit this. You can check it.
Thanks,
Adam




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