number of layers in Nanonote PCB

Adam Wang adam at
Tue Feb 23 02:31:44 EST 2010

Hi Ron,

On Tue, Feb 23, 2010 at 10:59 AM, Ron K. Jeffries <rjeffries at> wrote:
> I may have missed a response so will ask again.
> How many layers does the Nanonote PCB use?

Sorry for the late reply.
4 layers on Nanonote PCB, you can check AVT2 reference design [1].

> My guess is 4 layers for Nanonote.
> Carlos' SAKC board proto will use 2 layers.
> Good: lower cost
> But, could (??) result in EMI issues that affect FCC certification.

The YA & current AVT2 reference boards [2] are/should be all designed,
based or extended from BEN NN which passed FCC and CE. Although SAKC
is for more I/O extendable purposes. It's thus a bare board which is
under initial developing. Some parts chose is taken considerations
followed by BEN's solutions. Like LCD circuits partly. I think now the
first stage is to make this board all functionality workable prior to


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