SPI master-to-master bridge
werner at openmoko.org
Fri Jul 30 07:53:13 EDT 2010
A quick question for the FPGA experts: the 4720 can only act as SPI
master. Suppose we have a circuit that also wants to be master. We
would then need something that receives on one end, and pushes out
on the other.
To keep things simple, let's assume byte-sized data flows only in
one direction, and the receiver is faster than the sender. Their
SPI clocks are not synchronized. This means that there would have
to be a "data ready" signal, since SPI itself doesn't provide flow
control for the slave.
What would be the simplest/cheapest CPLD that could do this ? E.g.,
would a XC9536XL (36 macrocells, 800 gates) be capable enough ? If
yes, would there be many spare gates ?
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