GPIOs in the userspace (for FPGA programming)

Andrés Calderón andres.calderon at emqbit.com
Sat Mar 13 08:46:29 EST 2010


On Sat, Mar 13, 2010 at 8:15 AM, zhan han <zhanhan.cn at gmail.com> wrote:
> Hi Carlos,
> I don't have the hardware, so I really didn't test it yet :)
> The 0xB0010000 just mapped address, you need to check out the MIPS spec.
> And if you have the full datasheet, check the hardware address of
> these registers.
>

ups, sorry for the silly question. The error was the base address.
Soon the  Xilinx FPGA programmer (xc3sprog)  ported to the JZ47xx.

Thanks,

   Andrés Calderón
    Cel:     +57 (300) 275 3666
    Email: andres.calderon at emqbit.com
    Gtalk:  andresfcalderon at gmail.com
    Web:    www.emqbit.com

> On Sat, Mar 13, 2010 at 9:08 PM, Carlos Camargo <cicamargoba at gmail.com> wrote:
>> Hi zhan
>>
>> We've already used a similar code, but, w3e use 0xB0010000 as GPIO_BASE,
>> searchig on dingoo sample code, we found that  they (and you) change this
>> address to 0x001000, can you tell me why ?
>> Carlos
>>
>> On Sat, Mar 13, 2010 at 5:25 AM, zhan han <zhanhan.cn at gmail.com> wrote:
>>>
>>> Hi,
>>>
>>> Here is an example, but I don't have the hardware, so you need to do
>>> your own test.
>>> These just for demonstration, check mach-jz4740/regs.h and
>>> mach-jz4740/ops.h for GPIO functions
>>> and implement your own APIs.
>>>
>>> ----------------cut here---------------------------------------------
>>>
>>> #include <stdio.h>
>>> #include <stdlib.h>
>>> #include <unistd.h>
>>> #include <sys/types.h>
>>> #include <sys/stat.h>
>>> #include <fcntl.h>
>>> #include <sys/mman.h>
>>>
>>> #define MY_GPIO_PIN     10
>>> #define GPIO_BASE 0x10010000
>>> unsigned char *gpio_map_addr;
>>>
>>> #define REG32(addr)             *((volatile unsigned int *)(addr))
>>>
>>> #define GPIO_PXFUNC(n)  (gpio_map_addr + (0x48 + (n)*0x100)) /*
>>> Function Clear Register */
>>> #define GPIO_PXSELC(n)  (gpio_map_addr + (0x58 + (n)*0x100)) /* Select
>>> Clear Register */
>>> #define GPIO_PXDIRS(n)  (gpio_map_addr + (0x64 + (n)*0x100)) /*
>>> Direction Set Register */
>>> #define GPIO_PXDATS(n)  (gpio_map_addr + (0x14 + (n)*0x100)) /* Port
>>> Data Set Register */
>>> #define GPIO_PXDATC(n)  (gpio_map_addr + (0x18 + (n)*0x100)) /* Port
>>> Data Clear Register */
>>> #define GPIO_PXPIN(n)   (gpio_map_addr + (0x00 + (n)*0x100)) /* PIN
>>> Level Register */
>>>
>>> #define REG_GPIO_PXFUNC(n)      REG32(GPIO_PXFUNC((n)))
>>> #define REG_GPIO_PXSELC(n)      REG32(GPIO_PXSELC((n)))
>>> #define REG_GPIO_PXDIRS(n)      REG32(GPIO_PXDIRS((n)))
>>> #define REG_GPIO_PXDATS(n)      REG32(GPIO_PXDATS((n)))
>>> #define REG_GPIO_PXDATC(n)      REG32(GPIO_PXDATC((n)))
>>> #define REG_GPIO_PXPIN(n)       REG32(GPIO_PXPIN((n)))  /* PIN level */
>>>
>>> #define __gpio_port_as_output(p, o)             \
>>> do {                                            \
>>>    REG_GPIO_PXFUNC(p) = (1 << (o));            \
>>>    REG_GPIO_PXSELC(p) = (1 << (o));            \
>>>    REG_GPIO_PXDIRS(p) = (1 << (o));            \
>>> } while (0)
>>>
>>> #define __gpio_as_output(n)                     \
>>> do {                                            \
>>>        unsigned int p, o;                      \
>>>        p = (n) / 32;                           \
>>>        o = (n) % 32;                           \
>>>        __gpio_port_as_output(p, o);            \
>>> } while (0)
>>>
>>> #define __gpio_as_input(n)                      \
>>> do {                                            \
>>>        unsigned int p, o;                      \
>>>        p = (n) / 32;                           \
>>>        o = (n) % 32;                           \
>>>        __gpio_port_as_input(p, o);             \
>>> } while (0)
>>>
>>> #define __gpio_set_pin(n)                       \
>>> do {                                            \
>>>        unsigned int p, o;                      \
>>>        p = (n) / 32;                           \
>>>        o = (n) % 32;                           \
>>>        REG_GPIO_PXDATS(p) = (1 << o);          \
>>> } while (0)
>>>
>>> #define __gpio_clear_pin(n)                     \
>>> do {                                            \
>>>        unsigned int p, o;                      \
>>>        p = (n) / 32;                           \
>>>        o = (n) % 32;                           \
>>>        REG_GPIO_PXDATC(p) = (1 << o);          \
>>> } while (0)
>>>
>>> #define __gpio_get_port(p)      (REG_GPIO_PXPIN(p))
>>>
>>> #define __gpio_get_pin(n)                       \
>>> ({                                              \
>>>        unsigned int p, o, v;                   \
>>>        p = (n) / 32;                           \
>>>        o = (n) % 32;                           \
>>>        if (__gpio_get_port(p) & (1 << o))      \
>>>                v = 1;                          \
>>>        else                                    \
>>>                v = 0;                          \
>>>        v;                                      \
>>> })
>>>
>>> int do_memory_map() {
>>>  int fd;
>>>  fd = open("/dev/mem", O_RDWR| O_SYNC);
>>>  if (fd < 0) {
>>>    perror("Failed to open /dev/mem");
>>>    return fd;
>>>  }
>>>  gpio_map_addr = mmap(0, getpagesize(), PROT_READ|PROT_WRITE,
>>> MAP_SHARED, fd, GPIO_BASE);
>>>  if(!gpio_map_addr)
>>>        return -1;
>>>  return fd;
>>> }
>>>
>>> int main()
>>> {
>>>        int ret;
>>>        ret = do_memory_map();
>>>        if(ret < 0)
>>>                return ret;
>>>
>>>        __gpio_as_output(MY_GPIO_PIN);
>>>        __gpio_clear_pin(MY_GPIO_PIN);
>>>        __gpio_set_pin(MY_GPIO_PIN);
>>>        printf("%d\n", __gpio_get_pin(MY_GPIO_PIN));
>>>
>>> }
>>>
>>> ----------------end----------------------------------------------------
>>>
>>> 2010/3/13 Andrés Calderón <andres.calderon at emqbit.com>:
>>> > Hi,
>>> >
>>> > We are porting the xc3sprog[1] FPGA programes to the  SAKC, there are
>>> > some example of using the Jz472x GPIOs to userspace ?
>>> >
>>> > [1] http://sourceforge.net/projects/xc3sprog/
>>> >
>>> > BR,
>>> >
>>> >
>>> >    Andrés Calderón
>>> >    Cel:     +57 (300) 275 3666
>>> >    Email: andres.calderon at emqbit.com
>>> >    Gtalk:  andresfcalderon at gmail.com
>>> >    Web:    www.emqbit.com
>>> >
>>> > _______________________________________________
>>> > Qi Developer Mailing List
>>> > Mail to list (members only): developer at lists.qi-hardware.com
>>> > Subscribe or Unsubscribe:
>>> > http://en.qi-hardware.com/mailman/listinfo/developer
>>> >
>>>
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>>
>>
>>
>> --
>> Carlos Iván Camargo Bareño
>> Profesor Asistente
>> Departamento de Ingeniería Eléctrica y Electrónica
>> Universidad Nacional de Colombia
>> cicamargoba at unal.edu.co
>>
>> _______________________________________________
>> Qi Developer Mailing List
>> Mail to list (members only): developer at lists.qi-hardware.com
>> Subscribe or Unsubscribe:
>> http://en.qi-hardware.com/mailman/listinfo/developer
>>
>
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