First questions

Bas Wijnen wijnen at
Sun Mar 21 14:17:57 EDT 2010

On Sun, Mar 21, 2010 at 12:53:55PM -0500, Brian Stuart wrote:
> > Note that the CPU timer (COUNT/COMPARE CP0 registers) is not running.
> > For the system clock, you need the on-chip OS-timer.  Also, the RANDOM
> > register isn't very usable as a random counter, because it doesn't
> > increment every clock cycle, but only on a TLBWR instruction (which
> > makes it just as usable as tlb field manager).
> >
> Thanks for the tips.  Those are useful to know, especially since Inferno
> doesn't need to use the paging hardware, so I really won't be playing with
> the TLB at all.

It does need to use the paging hardware, unless it's permanently running
in kernel mode.  Mips has [k]useg from 00000000 to 80000000 in all
modes, which is paged and goes through the tlb.  Only the kernel is able
to access higher addresses, which (partly) access unpaged memory.

> >  When booting over USB, I must first load a small program (max 4 kB) into
> > the device's cache, which is executed there.  This program is used to
> > set up the SDRAM.  After that, the kernel is loaded into the now working
> > SDRAM.  Booting from nand, I expect the same sequence.
> Are you using the same first stage as usbboot, or did you write your own?

I "wrote" my own.  Most of the code in there is copied directly from
usbboot stage1.

> > As was mentioned, you may prefer to test using usbboot instead of
> > SD-card.
> I certainly agree for the quick modify/test/debug cycles.  But I do want to
> get to a point where I don't have to be tethered to boot as soon as I can.

So do I, but I don't want to take longer than I need to get there. ;-)

It is well possible to unsolder the pins as well, I already did that

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