Ingenic roadmap

Sébastien Bourdeauducq sebastien.bourdeauducq at
Sat May 15 09:29:24 EDT 2010

On Friday 14 May 2010 21:08:08 Ron K. Jeffries wrote:
> But the cost and performance of FPGAs
> that implement an SOC do NOT come close to meeting requirements
> for building a semi-mass produced consumer electronic gadget
> such as Nanonote.

The FPGA we use on the M1 board should runs the design (CPU+hardware 
accelerators+peripherals) at 100MHz and might have very approximately the 
capacity to hold 7 Ingenic SoCs. It's $50 in "engineering samples" devices 
(that we are using atm) and the price should fall for the final device and for 
larger quantities. It's not *so* bad.

Furthermore, the FPGA-based system is just a step, we should manufacture a 
chip once the code is stable enough.


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