where does one find this link?

Wolfgang Spraul wolfgang at sharism.cc
Wed Nov 10 08:57:18 EST 2010


Ron,

> I still have not found the discussion about LM32 vs
> SPARC that started this thread.

sorry it was a bit slow, there is something in Sebastien's
thesis, page 23-24
http://www.milkymist.org/thesis/thesis.pdf

(I'm just quoting from the thesis)

---
GRLIB

GRLIB [13] is a very professional and standard-compliant library
of SoC cores. The library features a comprehensive set of cores:
AMBA AHB/APB bus control elements, the LEON3 SPARC processor, a
32-bit PC133 SDRAM controller, a 32-bit PCI bridge with DMA, a
10/100/1000 Mb/s Ethernet MAC, 16/32/64-bit DDR SDRAM/DDR2 SDRAM
controllers and more.

However, its drawbacks are:

* Code complexity: GRLIB is written in VHDL and makes intensive use
of custom types, packages, generate statements, etc.

* Cores are not self-contained. GRLIB defines many "building blocks"
that are used everywhere else in the code, making it difficult to
re-use code in another project which is not based on GRLIB.

* Significant FPGA resource usage. A system comprising the LEON3
SPARC processor with a 2-way set-associative 16kB cache and no
memory management unit (MMU), the DDR SDRAM controller, a RS232
serial port, and an Ethernet 10/100 MAC uses 13264 FPGA look-up
tables (LUT). They map to 79% of the Virtex-4 XC4VLX25 FPGA. We have
carried out the test with the Xst synthesizer, Xilinx ISE 11.3, and
GRLIB 1.0.21-b3957 (GPL release) using the default provided synthesis
scripts. This undermines the possibility of adding hardware
acceleration cores. In [22], a significant resource usage was also
reported for an older version of LEON.

* Relatively low clock frequency. With the same parameters as above,
the maximum clock frequency is 84 MHz.

Because of these reasons, GRLIB was not retained.
---

Hope this helps, the whole thesis is actually a good read...
Wolfgang




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