Jtag logic analyzer
Carlos Camargo
cicamargoba at gmail.com
Fri Sep 17 09:08:47 EDT 2010
Hi
I'm thinking in the best way to create a test suite for SIE. We need to know
the signals in the current design its type (in, out, bidir) and the test
vectors.
Xilinx generates a PAD report file in cvs format (.pad), this file contain
the FPGA pin's function, name, type, this is the format for each pin:
P4,sram_data<7>,IOB,IO_L02P_3,BIDIR,LVCMOS25*,3,12,SLOW,NONE**,IFD,,LOCATED,,YES,NONE,
so we can know which signals, pins and signals'type are used for our
project.
For the test vectors we can generate a VCD file from verilog dumping just
the inputs:
$dumpvars(-1,clk,rst,uart_txd,uart_rxd);
$dumpfile("system_tb.vcd");
this file can be used for create the test vectors using urjtag.
Sebastien, Werner, Rafa, Andrés
Any comments?
--
Carlos Iván Camargo Bareño
Profesor Asistente
Departamento de Ingeniería Eléctrica y Electrónica
Universidad Nacional de Colombia
cicamargoba at unal.edu.co
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