Jtag logic analyzer

Carlos Camargo cicamargoba at gmail.com
Fri Sep 17 09:10:14 EDT 2010


> Xilinx generates a PAD report file in cvs format (.pad), this file contain
> the FPGA pin's function, name, type, this is the format for each pin:
In csv format sorry (_pad.csv)


Carlos Iván Camargo Bareño
Profesor Asistente
Departamento de Ingeniería Eléctrica y Electrónica
Universidad Nacional de Colombia
cicamargoba at unal.edu.co
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