Jtag logic analyzer
Carlos Camargo
cicamargoba at gmail.com
Fri Sep 17 11:20:35 EDT 2010
Sebastien you mean build a test block with the UUT, and using this
test_block to report the results?
Carlos
On Fri, Sep 17, 2010 at 8:56 AM, Sébastien Bourdeauducq <
sebastien.bourdeauducq at lekernel.net> wrote:
> Why not develop a test bitstream and load it into the fpga instead of
> using JTAG (which is slow)?
>
> S.
>
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--
Carlos Iván Camargo Bareño
Profesor Asistente
Departamento de Ingeniería Eléctrica y Electrónica
Universidad Nacional de Colombia
cicamargoba at unal.edu.co
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