test point map

Werner Almesberger werner at almesberger.net
Wed Jun 8 20:38:39 EDT 2011


I think we didn't have a map illustrating what the various test points
on the Ben's PCB are connected to yet. Well, here's a start:

http://downloads.qi-hardware.com/people/werner/tmp/tp-map-ba.png

And this table explains what SoC subsystems connect to the TPs, and
what they could be used for if one would "export" them:

http://projects.qi-hardware.com/index.php/p/wernermisc/source/tree/master/tp/MAP

This is only the battery area. There are about two dozen more TPs
scattered all over the board.

Note that accessing some of the TPs is tricky. It's easy enough to
solder little wires to them (two are visible in the picture), but
if you want to use a board with spring-loaded pins, similar to
atusb-pgm

http://downloads.qi-hardware.com/people/werner/wpan/tmp/atusb-programming.jpg

then the spacing between some of the test points would be too
tight for individual pins (which need about a 2.0 mm spacing) and
just not the right distance for pin arrays (which can go as small
as 50 mil / 1.27 mm).

- Werner




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