ubb-vga: 640x480 without FIFO jitter; less noise

Werner Almesberger werner at almesberger.net
Tue May 3 11:47:19 EDT 2011

So far, when using DMA, all the 640x480 modes suffered from what I
call FIFO jitter, where many lines are shifted by 10-20 pixels,
similar to the artefacts shown here:


I now cooked up a new mode called 640x480/61 that doesn't always do
this. It still has a probablility of about 30% of suffering FIFO
jitter during an entire session, but if a session starts cleanly,
it stays clean.

Here is what it looks like on my 1680x1050 Samsung:

I also tweaked the clocks a bit to make the MMC controller run faster
than the bus clock whenever possible. This may also have helped to
improve the chance of getting a stable image.

As one can see, there is still considerable jitter in the range of a
few pixels. I suspected that this was caused by the low accuracy of
my timer polling loop: the timer runs at about 112 MHz but we can
only poll it with approximately 10 MHz.

To try to compensate for this, I changed the timer function to read
the current (112 MHz) timer value at the end of the wait, and to run
a delay loop for the difference between this value and a fixed point
a bit further ahead.

For example, if we waited for time TCNT = 1000, we would detect that
the timer has crossed that value at TCNT = 1000+n, with n between 0
and 20. If we set the real deadline to 1000+24, the loop would then
run for the difference between 1024 and the value read from the timer
register, multiplied with a suitable scale factor.

This turned out to work quite well:


Next, I examined the hsync signal with a scope and plotted the
statistical distribution of the signal edges:


Trigger is on the falling edge. Red means there was often a sample
at this point, green a bit less, blue rarely, black never.

- Werner

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