Anelok: oscillator choices

Felix sucotronic at gmail.com
Wed Jun 4 06:53:36 EDT 2014


For usb 1.1 low speed only 6mhz are need, but nowadays all is 2.0...curious
to see why they don't offer low speed usb options....


On Mon, Jun 2, 2014 at 1:07 PM, Werner Almesberger <werner at almesberger.net>
wrote:

> Felix wrote:
> > Wow, it's the first time I hear of FLL generators, but the idea seems
> good
> > enough to use a low power crystal for main clk source :D
>
> Even the Wikipedia article is rather terse :)
> en.wikipedia.org/wiki/Frequency-locked_loop
>
> > Btw, the jitter is too much for certification, but, how much is the
> > tolerance of usb controllers chips? Will they be able to handle it?
>
> According to the data sheet (dsv kl26, page 25), the FLL has a period
> jitter of 180 ps at 48 MHz. (With the PLL, we need to run at 96 MHz
> to obtain the 48 MHZ USB clock because there's a mandatory /2 divider
> in the clock path. When using the FLL there's no such divider.)
>
> The USB specification 2.0 (dsv usb, page 181) states that full-speed
> sources shouldn't jitter by more than -2/+3.5 ns (Worst-case values,
> Tfdeop(min) and Tdj1(max).) Receivers have even more tolerant timing.
>
> I don't know what the certification requirements are. The checklists
> on http://www.usb.org/developers/compliance/low_full/
> don't even mention jitter. The test procedures in
>
> http://www.usb.org/developers/compliance/electrical_tests/USB-IFTestProc1_3.pdf
> do mention jitter but don't say what is acceptable.
>
> - Werner
>
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-- 
Felix
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